This invention relates to a method of communication between processors.
Numerous techniques have been developed for processor-to-processor communications using multiple byte messages. Usually, a master/slave relationship is established for the two processors to avoid bus contention problems and multiple byte messages are either exchanged in their entirety with processor interrupts disabled or on a byte-by-byte basis using some type of hardware feedback mechanism which allows the slave to notify the master when it is ready for another byte.
These communication techniques work well, but do have their drawbacks. The first technique requires interrupt suppression for the duration of the message exchange. This may not be a problem in some systems, but as message lengths increase and interrupt timing becomes critical, prolonged interrupt suppression may not be acceptable since processor throughput is limited by the interrupt suppression time. The second technique can be interrupt driven. This eliminates prolonged interrupt suppression as message lengths increase, but requires the use of additional processor I/O lines which are often needed for other purposes.